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Advanced
CAT25C03/05/09/17/33
2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES
s 10 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP s Page Write Buffer s Write Protection
Temperature Ranges
- Protect First Page, Last Page, Any 1/4 Array or Lower 1/2 Array
DESCRIPTION
The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25C03/05 features a 16-byte page write buffer. The 25C09/17/33 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C03/05/09/17/33 is designed with software and hardware write protection features. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP packages.
PIN CONFIGURATION
TSSOP Package (U14) SOIC Package (S16) SOIC Package (S) DIP Package (P)
CS SO NC NC NC WP VSS
TSSOP Package (U)
1 2 3 4 8 7 6 5 VCC HOLD SCL SI
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC HOLD NC NC NC SCK SI
CS SO NC NC NC NC WP VSS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC HOLD NC NC NC NC SCK SI
CS SO WP VSS
1 2 3 4
8 7 6 5
VCC CS HOLD SO SCK WP SI
1 2 3 4
VSS
8 7 6 5
VCC CS HOLD SO SCK SI
WP VSS
BLOCK DIAGRAM
SENSE AMPS SHIFT REGISTERS
PIN FUNCTIONS Pin Name
SO SCK WP VCC VSS CS SI HOLD NC
WORD ADDRESS BUFFERS
COLUMN DECODERS
Function
Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect
STATUS REGISTER HIGH VOLTAGE/ TIMING CONTROL
25C128 F02
SO SI CS WP HOLD SCK
I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC
CONTROL LOGIC
XDEC
E2PROM ARRAY
DATA IN STORAGE
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25C03/05/09/17/33
Advanced
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to Ground(1) ............ -2.0V to +VCC +2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VIL(3) VIH(3) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC - 0.8 0.2 -1 VCC x 0.7 Min. Typ. Max. 5 0.4 0 2 3 VCC x 0.3 VCC + 0.5 0.4 Units mA mA A A A V V V V V V 4.5VVCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8VVCC<2.7V IOL = 150A IOH = -100A VOUT = 0V to VCC, CS = 0V Test Conditions VCC = 5V @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK = 5MHz CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
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CAT25C03/05/09/17/33
Figure 1. Sychronous Data Timing
VIH
tCS
CS
VIL tCSS VIH tCSH
SCK
VIL tSU VIH
tWH tH
tWL
SI
VIL
VALID IN
tV VOH
tHO
tDIS HI-Z
SO
VOL
HI-Z
A.C. CHARACTERISTICS Limits 1.8, 2.5 SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI tFI
(1)
4.5V-5.5V Min. 10 20 40 40 2 50 2 2 DC 10 50 2 2 40 40 10 200 5 80 0 250 100 75 50 100 100 100 Max. ns ns ns ns MHz ns s s ns ns ms ns ns ns ns ns ns ns
Test UNITS Conditions VIH = 2.4V CL = 100pF VOL = 0.8V VOH = 2.0v
Min. 50 50 200 200 DC
Max.
Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD HOLD Time Write Cycle Time Output Valid from Clock Low Output HOLD Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS HOLD Time
CL = 50pF
(1)
tHD tCD tWC tV tHO tDIS tHZ tCS tCSS tCSH
100 100
CL = 100pF
0
250 250 250
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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FUNCTIONAL DESCRIPTION
The CAT25C03/05/09/17/33 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C03/05/09/17/33 to interface directly with many of today's popular microcontrollers. The CAT25C03/05/09/17/33 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed.
and the 25C03/05/09/17/33. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. CS Chip Select CS: CS is the Chip select pin. CS low enables the CAT25C03/ 05/09/17/33 and CS high disables the CAT25C03/05/ 09/17/33. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C03/05/09/17/33 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP Write Protect WP: WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all write operations to the device are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. HOLD: HOLD Hold HOLD is the HOLD pin. The HOLD pin is used to pause transmission to the CAT25C03/05/09/17/33 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be
PIN DESCRIPTION
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C03/05/09/17/33. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C03/05/09/17/33. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Power-Up Timing(2)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011(1) 0000 X010(1)
Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
Max. 1 1
Units ms ms
Note: (1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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CAT25C03/05/09/17/33
brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence.
STATUS REGISTER
The status register defines the protection status of the device. The register features three protection bits which allow the user to protect the desirable part of the memory array. There are seven different variations for the protection mechanism. The protection can vary from one page to as much as half of the entire array. These areas and associated address ranges are protected by configuring the protection bits of the status register through WRSR instruction. Once the three protection bits are set, the associated memory can be read but not written until the protection bits are reset.
STATUS REGISTER 7 0 6 0 5 0 4 0 3 0 2 IDL2 1 IDL1 0 IDL0
MEMORY PROTECTION IDL2 0 0 0 0 1 1 1 1 IDL1 0 0 1 1 0 0 1 1 IDL0 0 1 0 1 0 1 0 1 Non-Protection Q1 Protected Q2 Protected Q3 Protected Q4 Protected H1 Protected P0 Protected Pn Protected
25C03 Q1 Q2 Q3 Q4 H1 P0 Pn 00-3F 40-7F 80-BF C0-FF 00-7F 00-0F F0-FF
25C05
25C09
25C17 000-1FF 200-3FF 400-5FF 600-7FF 000-3FF 000-01F
25C33 000-3FF 400-7FF 800-BFF C00-FFF 000-7FF 000-01F
000-07F 000-0FF 080-0FF 100-1FF 100-17F 200-2FF 180-1FF 300-3FF 000-0FF 000-1FF 000-00F 000-01F
1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF
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Advanced
DEVICE OPERATION
Write Enable and Disable The CAT25C03/05/09/17/33 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C03/05/09/17/33, followed by the 16-bit address for 25C09/17/33 (only 10bit addresses are used for 25C09, 11-bit addresses are used for 25C17, and 12-bit addresses are used for 25C33. The rest of the bits are don't care bits) and 8-bit address for 25C03/05 (for the 25C05, bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. If a non-volatile write is in progress, the RDSR instruction returns a high on SO. When the non-volatile write cycle is completed, the status register data is read out.
Figure 2. WREN Instruction Timing
SK
CS
SI
0
0
0
0
0
1
1
0
SO
HIGH-Z
Figure 3. WRDI Instruction Timing
SK
CS
SI
0
0
0
0
0
1
0
0
SO
HIGH-Z
25C128 F05
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CAT25C03/05/09/17/33
WRITE Sequence The CAT25C03/05/09/17/33 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C03/05/09/17/33. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C03/05/09/17/33. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field. Figure 4. Read Instruction Timing
RESET 0 SK 1 2 3 4 5 6 7 8 9 10
Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address for 25C09/17/33. (only 10-bit addresses are used for 25C09, 11-bit addresses are used for 25C17, and 12-bit addresses are used for 25C33. The rest of the bits are don't care bits) and 8-bit address for 25C03/05 (for the 25C05, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. The low to high transition of the CS pin must occur during the SCK low time, immediately after clocking the least significant bit of the data. Figure 6 illustrates byte write sequence.
20
21
22
23
24
25
26
27
28
29
30
CS
SI
0
0
0
0
0
0
1
1
BYTE ADDRESS*
SO
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
Figure 5. RDSR Timing
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI DATA OUT SO HIGH IMPEDANCE 7 MSB
25C03 F09
6
5
4
3
2
1
0
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Advanced
Page Write The CAT25C03/05/09/17/33 features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C03/05 and 32 bytes of data for 25C09/17/33. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address willremain constant.The only restriction is that the X (X=16 for 25C03/05 and X=32 for 25C09/17/33) bytes must reside on the same page. If the address counter
reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25C03/05/09/17/33 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Figure 7 illustrates the sequence of writing to status register.
Figure 6. Write Instruction Timing
0 SK
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
CS
SI
0
0
0
0
0
0
1
0
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
SO
Figure 7. WRSR Timing
CS 0 SCK DATA IN 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION SI
SO
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CAT25C03/05/09/17/33
DESIGN CONSIDERATIONS The CAT25C03/05/09/17/33 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C03/05/09/17/33 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle Figure 8. Page Write Instruction Timing is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C03/05/ 09/17/33, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
0 SK
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
CS
SI
0
0
0
0
0
0
1
0
ADDRESS
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte N
SO
Figure 9. HOLD Timing
CS tCD SCK tHD HOLD tHZ SO tLZ
25C128 F10
tCD
tHD
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CAT25C03/05/09/17/33
Advanced
ORDERING INFORMATION Prefix CAT Device # 25C17 Suffix S I Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40 to +105C)* -1.8 TE13
Optional Company ID
Product Number 25C33: 32K 25C17:16K 25C09: 8K 25C05: 4K 25C03: 2K
Tape & Reel TE13: 2000/Reel
Package P = PDIP S = 8-pin SOIC S16 = 16-pin SOIC U=8-pin TSSOP U14 = 14-pin TSSOP
Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V)
* -40C to +125C is available upon request
Notes: (1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel)
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